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MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 1 description the mh1s64cwxtj is 1048576-word by 64-bit synchronous dram module. this consists of four industry standard 1mx16 synchronous drams in tsop and one industory standard eeprom in tssop. the mounting of tsop on a card edge dual inline package provides any application where high densities and large quantities of memory are required. this is a socket type - memory modules, suitable for easy interchange or addition of modules. features clock frequency 83mhz/67mhz single 3.3v?.3v power supply fully synchronous operation referenced to clock rising edge burst length- 1/2/4/8(programmable) dual bank operation controlled by ba(bank address) /cas latency- 1/2/3(programmable) application main memory or graphic memory in computer systems auto precharge / all bank precharge controlled by a10 burst type- sequential / interleave(programmable) column access - random lvttl interface auto refresh and self refresh 4096 refresh cycle /64ms 1pin 10pin 11pin 40pin 41pin 84pin front side 85pin 94pin 95pin 124pin 125pin 168pin back side utilizes industry standard 1m x 16 synchronous drams tsop and industry standard eeprom in tssop 168-pin (84-pin dual in-line package) frequency -1539 67mhz clk access time 9ns (cl=3) -12 83mhz 8ns(cl=3) -15 67mhz 9.5ns (cl=2) (component sdram) MH1S64CWXTJ-12 byte no. 0 1 2 3 4 5 6 7 8 9 10 11 12 80 08 04 0c 08 01 40 00 01 c0 80 00 80 80 08 04 0c 08 01 40 00 01 f0 95 00 80 mh1s64cwxtj-15 13 00 00 14 06 06 15 01 01 16 05 05 17 02 02 18 06 06 19 01 01 20 01 01 126 83 66 127 06 06 spd table 80 08 04 0c 08 01 40 00 01 f0 90 00 80 mh1s64cwxtj-1539 00 04 01 05 02 04 01 01 66 04
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 2 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 43 vss 85 vss 127 vss 2 dq0 44 nc 86 dq32 128 cke 3 dq1 45 /s2 87 dq33 129 nc 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 vdd 48 nc 90 vdd 132 nc 7 dq4 49 vdd 91 dq36 133 vdd 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 nc 94 dq39 136 nc 11 dq8 53 nc 95 dq40 137 nc 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vdd 101 dq45 143 vdd 18 vdd 60 dq20 102 vdd 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 nc 63 nc 105 nc 147 nc 22 nc 64 vss 106 nc 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vdd 68 vss 110 vdd 152 vss 27 /we 69 dq24 111 /cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 /s0 72 dq27 114 nc 156 dq59 31 nc 73 vdd 115 /ras 157 vdd 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 nc 121 a9 163 nc 38 a10 80 nc 122 ba 164 nc 39 nc 81 nc 123 nc 165 sa0 40 vdd 82 sda 124 vdd 166 sa1 41 vdd 83 scl 125 nc 167 sa2 42 ck0 84 vdd 126 nc 168 vdd nc = no connection pin configuration
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 3 block diagram clk cs ras cas we cke d0 dq1 dq0 dq2 dq3 dq4 dq5 dq6 dq7 dq33 dq32 dq34 dq35 dq36 dq37 dq38 dq39 dq41 dq40 dq42 dq43 dq44 dq45 dq46 dq47 dq49 dq48 dq50 dq51 dq52 dq53 dq54 dq55 dq57 dq56 dq58 dq59 dq60 dq61 dq62 dq63 dq25 dq24 dq26 dq27 dq28 dq29 dq30 dq31 dq17 dq16 dq18 dq19 dq20 dq21 dq22 dq23 dq9 dq8 dq10 dq11 dq12 dq13 dq14 dq15 dqmb4 dqmb1 dqmb5 dqmb2 dqmb6 dqmb3 dqmb7 d4 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 d2 d3 d2 d1 dqmb0 /ras /cas /we cke a0 a1 a2 sda scl serial pd vcc vss d0 to d3 d0 to d3 ck0 ba,a(10:0) d0 to d3 dqmu dqmu dqmu dqmu dq0~dq7 dq8~dq15 dq0~dq7 dq8~dq15 dq0~dq7 dq8~dq15 dq0~dq7 dq8~dq15 sa0 sa1 sa2 /s2 /s0 clk cs ras cas we cke clk cs ras cas we cke clk cs ras cas we cke dqml dqml dqml dqml
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 pin function input master clock:all other inputs are referenced to the rising edge of ck cke input clock enable:cke controls internal clock.when cke is low,internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke e becomes asynchronous input.self refresh is maintained as long as cke is low. /s (/s0 &/s2) input chip select: when /s is high,any command means no operation. /ras,/cas,/we input combination of /ras,/cas,/we defines basic commands. a0-10 input a0-10 specify the row/column address in conjunction with ba.the row address is specified by a0-10.the column address is specified by a0-7.a10 is also used to indicate precharge option.when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, both banks are precharged. ba input bank address:ba is not simply ba.ba specifies the bank to which a command is applied.ba must be set with act,pre,read,write commands dq0-63 input/output data in and data out are referenced to the rising edge of ck dqmb0-7 input din mask/output disable:when dqmb is high in burst write.din for the current cycle is masked.when dqmb is high in burst read,dout is disabled at the next but one cycle. vdd,vss power supply power supply for the memory mounted module. sla sda input output serial clock for serial pd serial data for serial pd 4 ck (ck0)
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 basic functions /s chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command ck define basic commands the mh1s64cwxtj provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. each command is defined by control signals of /ras,/cas and /we at ck rising edge. in addition to 3 signals,/s,cke and a10 are used as chip select,refresh option,and precharge option,respectively. to know the detailed definition of commands please see the command truth table. activate(act) [/ras =l, /cas = /we =h] read(read) [/ras =h,/cas =l, /we =h] write(write) [/ras =h, /cas = /we =l] precharge(pre) [/ras =l, /cas =h,/we =l] auto-refresh(refa) [/ras =/cas =l, /we =cke =h] act command activates a row in an idle bank indicated by ba. read command starts burst read from the active bank indicated by ba.first output data appears after /cas latency. when a10 =h at this command,the bank is deactivated after the burst read(auto-precharge, reada ). write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write(auto-precharge, writea ). pre command deactivates the active bank indicated by ba. this command also terminates burst read / write operation. when a10 =h at this command, both banks are deactivated(precharge all, prea ). pefa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. 5
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 command truth table command mnemonic ck n-1 ck n /s /ras /cas /we ba a10 a0-9 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row adress entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all bank prea h x l l h l v h x column address entry & write write h x l lh h l v l v column address entry & write with auto- precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto precharge reada h x l h l h v h v auto-refresh refa h h l hl l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h lx x x x x x l h l h h h x x x burst terminate term h x l h h l x x x mode register set mrs h x l l l l l l v*1 h =high level, l = low level, v = valid, x = don't care, n = ck cycle number note: 1.a7-9 = 0, a0-6 = mode address 6
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 current state /s /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act bank active,latch ra l l h l ba,a10 pre/prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l ba tbst nop l h l h ba,ca,a10 read/reada begin read,latch ca, determine auto-precharge l h l l ba,ca,a10 write/ writea begin write,latch ca, determine auto-precharge l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea precharge/precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba tbst terminate burst l h l h ba,ca,a10 read/reada terminate burst,latch ca, begin new read,determine auto-precharge*3 l h l l ba,ca,a10 write/writea terminate burst,latch ca, begin write,determine auto- precharge*3 l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea terminate burst,precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal function truth table 7
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 function truth table (continued) current state /s /ras /cas /we address command action write h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba tbst terminate burst l h l h ba,ca,a10 read/reada terminate burst,latch ca, begin read,determine auto- precharge*3 l h l l ba,ca,a10 write/ writea terminate burst,latch ca, begin write,determine auto- precharge*3 l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea terminate burst,precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with h x x x x desel nop(continue burst to end) auto l h h h x nop nop(continue burst to end) precharge l h h l ba tbst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 write/ writea illegal l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with h x x x x desel nop(continue burst to end) auto l h h h x nop nop(continue burst to end) precharge l h h l ba tbst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 write/ writea illegal l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal 8
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 function truth table (continued) current state /s /ras /cas /we address command action pre - h x x x x desel nop(idle after trp) charging l h h h x nop nop(idle after trp) l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea nop*4(idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row h x x x x desel nop(row active after trcd activating l h h h x nop nop(row active after trcd l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- h x x x x desel nop covering l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal 9
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 function truth table (continued) current state /s /ras /cas /we address command action re- h x x x x desel nop(idle after trc) freshing l h h h x nop nop(idle after trc) l h h l ba tbst illegal l h l x ba,ca,a10 read/write illegal l l h h ba,ra act illegal l l h l ba,a10 pre/prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode h x x x x desel nop(idle after trsc) register l h h h x nop nop(idle after trsc) setting l h h l ba tbst illegal l h l x ba,ca,a10 read/write illegal l l h h ba,ra act illegal l l h l ba,a10 pre/prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h = hige level, l = low level, x = don't care ba = bank address, ra = row address, ca = column address, nop = no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state.may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and / or date-integrity are not guaranteed. 10
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 function truth table for cke current state ck n-1 ck n /s /ras /cas /we add action self - h x x x x x x invalid refresh*1 l h h x x x x exit self-refresh(idle after trc) l h l h h h x exit self-refresh(idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self-refresh) power h x x x x x x invalid down l h x x x x x exit power down to idle l l x x x x x nop(maintain self-refresh) all banks h h x x x x x refer to function truth table idle*2 h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state = power down any state h h x x x x x refer to function truth table other than h l x x x x x begin ck0 suspend at next cycle*3 listed above l h x x x x x exit ck0 suspend at next cycle*3 l l x x x x x maintain ck0 suspend abbreviations: h = high level, l = low level, x = don't care notes: 1. cke low to high transition will re-enable ck and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only form the all banks idle state. 3. must be legal command. 11
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 simplified state diagram row active idle pre charge auto refresh self refresh mode register set power down read reada write writea read suspend reada suspend write suspend writea suspend power on clk suspend ckel ckeh ckel ckeh ckel ckeh ckel ckeh act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada write read pre reada writea reada pre pre pre power applied automatic sequence command sequence 12
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqmb0-7 high and nop condition at the inputs. 2. maintain stable power, stable cock, and nop input conditions for a minimum of 500? s. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 ltmode bt bl bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 1 2 4 8 r r r r 1 2 4 8 r r r r 0 1 burst type sequential interleaved cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 latency mode /cas latency 1 2 3 r r r r r r:reserved for future use /s /ras /cas /we ba, a10 -a0 ck v burst length, burst type and /cas latency can be programmed by setting the mode register(mrs). the mode register stores these date until the next mrs command, which may be issue when both banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. 13
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 command address ck read y q0 q1 q2 q3 write y d0 d1 d2 d3 /cas latency burst length burst length dq burst type cl= 3 bl= 4 a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 14
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 bank activation and precharge all (bl=4, cl=3) ck command a0-9 a10 ba dq act xa xa 0 read y 0 0 qa0 qa1 qa2 qa3 act xb xb 1 pre trrd trcd 1 act xb xb 1 precharge all tras trp operation description bank activate the sdram has two independent banks. each bank is activated by the act command with the bank address(ba). a row is indicated by the row address a10-0. the minimum activation interval between one bank and the other bank is trrd. precharge the pre command deactivates indicated by ba. when both banks are active, the precharge all command(prea,pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command can be issued. read after trcd from the bank activation, a read command can be issued. 1st output date is available after the /cas latency from the read, followed by (bl-1) consecutive date when the burst length is bl. the start address is specified by a7-0, and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time(trp) can be hidden behind continuous output data(in case of bl=8) by interleaving the dual banks. when a10 is high at a read command, the auto-precharge(reada) is performed. any command (read, write, pre, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge start timing depends on /cad latency. the next act command can be issued after trp from the internal precharge timing. 15
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 dual bank interleaving read (bl=4, cl=3) ck command a0-9 a10 ba dq act xa xa 0 read y 0 0 read y 0 1 qa0 qa1 qa2 qa3 qb0 qb1 qb2 act xb xb 1 pre 0 0 trcd /cas latency burst length read with auto-precharge (bl=4, cl=3) ck command a0-9 a10 ba dq act xa xa 0 read y 1 0 qa0 qa1 qa2 qa3 act xa xa 0 internal precharge begins trcd trp read auto-precharge timing (bl=4) ck command act read internal precharge start timing dq qa0 qa1 qa2 qa3 dq qa0 qa1 qa2 qa3 cl=3 cl=2 16 dq qa0 qa1 qa2 qa3 cl=1
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 dual bank interleaving write (bl=4) ck command a0-9 a10 ba dq act xa xa 0 write y 0 0 write y 0 1 da0 da1 da2 da3 act xb xb 1 pre 0 0 trcd burst length db0 db1 db2 db3 trcd twr ck command a0-9 a10 ba dq act xa xa 0 write y 1 0 da0 da1 da2 da3 act xa xa 0 internal precharge begins trcd trp twr write with auto-precharge (bl=4) write after trcd from the bank activation, a write command can be issued. 1st input data is set at the same cycle as the write. following(bl-1) data are written into the ram, when the burst length is bl. the start address is specified by a7-0, and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time(trp) can be hidden behind continuous input data (in case of bl=4) by interleaving the dual banks. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read, write, pre, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge begins at twr after the last input data cycle. the next act command can be issued after trp from the internal precharge timing. 17
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 burst interruption [ read interrupted by read ] burst read option can be interrupted by new read of the same or the other bank. mh4s64ctj allows random column access. read to read interval is minimum 1 ck read interrupted by read (bl=4, cl=3) ck command a0-9 a10 ba dq read yi 0 0 read yk 0 1 qai0 qaj1 qbk0 qbk1 read yj 0 0 qaj0 qbk2 qal0 read yl 0 0 qal1 qal2 qal3 [ read interrupted by write ] burst read operation can be interrupted by write of the same or the other bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqmb0-7 to prevent the bus contention. the output is disabled automatically 2 cycle after write assertion. read interrupted by write (bl=4, cl=3) ck command a0-9 a10 ba q read yi 0 0 qai0 write yj 0 0 d daj0 daj1 daj2 daj3 dqmb0-7 dqm control write control 18
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same or the other bank. read to pre interval is minimum 1 ck. a pre command disables the data output, depending on the /cas latency. the figure below shows examples, when the dataout is terminated. read interrupted by precharge (bl=4) ck command dq read pre q0 q2 q3 q1 command dq read q0 q1 command dq read pre q0 q1 command dq read pre q0 q1 command dq read pre q0 q2 q3 q1 command dq read pre q0 q1 pre q2 q3 cl=4 cl=3 cl=2 comman d dq rea d pre q 0 q 2 q 3 q 1 comman d dq rea d pr e q 0 q 1 cl= 1 19
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 [ read interrupted by burst terminate ] similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. read to term interval is minimum 1 ck. the figure below shows examples, when the dataout is terminated. read interrupted by burst terminate (bl=4) ck command dq read term q0 q1 q2 q3 cl=3 command dq read term q0 q1 q2 command dq read term q0 command dq read term q0 q1 q2 q3 cl=2 command dq read term q0 q1 q2 command dq read term q0 command dq read term q0 q1 q2 q3 cl=1 command dq read term q0 20
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 [ write interrupted by write ] burst write operation can be interrupted by new write of the same or the other bank. random column access is allowed. write to write interval is minimum 1 ck. write interrupted by write (bl=4) ck command a0-9 a10 ba dq write yi 0 0 write yk 0 1 dai0 daj0 daj1 dbk0 write yj 0 0 dbk1 dbk2 write yl 0 0 dal0 dal1 dal2 dal3 [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 ck. the input data on dq at the interrupting read cycle is "don't care". write interrupted by read (bl=4, cl=3) ck command a0-9 a10 ba dq write yi 0 0 qaj0 read yj 0 0 qaj1 dai0 dak0 dak1 dqmb0-7 write yk 0 0 read yl 0 1 qbl0 21
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank. random column access is allowed. because the write recovery time(twr) is required between the last input data and the next pre, 3rd data should be masked with dqmb0-7 shown as below. write interrupted by precharge (bl=4) ck command a0-9 a10 ba dq write yi 0 0 pre 0 0 dai0 dai1 dqmb0-7 act xb xb 0 twr trp this data should be masked to satisfy twr requirement. [ write interrupted by burst terminate ] burst terminate command can terminate burst write operation. in this case, the write recovery time is not required and the bank remains active. the figure below shows the case 3 words of data are written. random column access is allowed. write to term interval is minimum 1 ck. write interrupted by burst terminate (bl=4) ck command a0-9 a10 ba dq write yi 0 0 term dai0 dai1 dqmb0-7 dai2 22
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 auto refresh single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l, /we=/cke=h) command. the refresh address is generated internally. 4096 refa cycle within 64ms refresh 16mbit memory cells. the auto-refresh is performed on each bank alternately(ping-pong refresh). before performing an auto-refresh, both banks must be in the idle state. additional commands must not be supplied to the device before trc from the refa command. auto-refresh ck /s /ras /cas /we cke a0-10 ba auto refresh on bank 0 auto refresh on bank 1 minimum trc nop or deslect 23
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 self refresh self-refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l, /we=h, cke=l). once the self-refresh is initiated, it is maintained as log as cke is kept low.during the self-refresh mode, cke is asynchronous and the only enabled input (but asynchronous), all other inputs including ck0 are disabled and ignored, and power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable ck0 inputs, asserting desel or nop command and then asserting cke(refsx). after trc from refsx both banks are in the idle state and a new command can be issued after trc, but desel or nop commands must be asserted till then. self-refresh ck /s /ras /cas /we cke a0-10 ba self refresh entry self refresh exit x 0 minimum trc for recovery stable ck nop new command 24
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored. ck (ext.clk) cke int.clk power down by cke ck command pre cke command cke act nop nop nop nop nop nop nop nop nop nop nop nop standby power down active power down nop nop dq suspend by cke ck command dq write d0 d1 d2 d3 cke read q0 q1 q2 q3 25
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 dqm control dqmb0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqmb0-7 masks input data word by word. dqmb0-7 to write mask latency is 0. during reads, dqmb0-7 forces output to hi-z word by word. dqmb0-7 to output hi-z latency is 2. dqm function ck command dq write d0 d2 d3 dqmb0-7 read q0 q1 q3 masked by dqm=h disabled by dqm=h 26
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 absolute maximum ratings symbol parameter condition ratings unit vdd vi vo io pd topr tstg supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature with respect to vss with respect to vss with respect to vss ta=25? -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 4 0 ~ 70 -40 ~ 100 v v v ma w ? ? recommended operating condition (ta=0 ~ 70?, unless otherwise noted) symbol vdd vss vih vil parameter supply voltage high-level input voltage all inputs supply voltage low-level input voltage all inputs limits unit min. typ. max. 3.0 0 2.0 -0.3 3.3 0 3.6 0 vdd+0.3 0.8 v v v v capacitance (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) symbol ci(a) ci(c) ci(k) ci/o parameter input capacitance, address pin input capacitance, control pin input capacitance, ck pin input capacitance, i/o pin test condition limits(max.) unit vi = vss f=1mhz vi=25mvrms 30 30 15 12 pf pf pf pf 27
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 average supply current from vdd (ta=0 ~70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) symbol parameter test condition limits unit min. max. voh(dc) high-level output voltage(dc) ioh=-2ma 2.4 v vol(dc) low-level output voltage(dc) iol=2ma 0.4 v voh(ac ) high-level output voltage(ac) cl=50pf, ioh=-2ma 2 v vol(ac) low-level output voltage(ac) cl=50pf, iol=2ma 0.8 v 360 300 520 440 72 64 8 8 140 120 480 400 240 200 4 4 28 ioz off-stare output current q floating vo=0 ~ vdd -10 10 ua ii input current vih=0 ~ vdd+0.3v -40 40 ua symbol parameter test condition limits(max) unit -12 -15 -1539 icc1s operating current, single bank trc=min.tclk=min, bl=1, cl=3 ma icc1d operating current, dual bank trc=min.tclk=min, bl=1, cl=3 icc2h standby current, cke=h both banks idle, tclk=min, cke=h ma icc2l standby current, cke=l both banks idle, tclk=min, cke=l ma icc3 active standby current ma icc4 burst current tclk=min, bl=4, cl=3, 1 bank idle(discerte) ma icc5 auto-refresh current trc=min, tclk=min ma icc6 self-refresh current cke <0.2v ma both banks active, tclk=min, cke=h ma 360 520 72 8 140 480 240 4
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 ac timing requirements (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) input pulse levels: 0.8v to 2.0v input timing measurement level: 1.4v ck signal 1.4v 1.4v any ac timing is referenced to the input signal crossing through 1.4v. 29 max. limits symbol parameter -15 -1539 unit min. max. min. max. 30 30 ns tclk ck cycle time 15 20 ns 15 ns tch ck high pulse width 4 12 4 ns tcl ck low pilse width 4 4 ns tt transition time of ck 1 10 1 10 ns tis input setup time(all inputs) 3 3 ns tih input hold time(all inputs) 1 1.5 ns trc row cycle time 100 120 ns trcd row to column delay 30 30 ns tras row active time 70 10000 80 10000 ns trp row precharge time 30 40 ns twr write recovery time 12 15 ns trrd act to act deley time 24 30 ns trsc mode register set cycle time 24 30 ns tpde power down exit time 12 15 ns tref refresh interval time 65.6 65.6 ms cl=1 cl=2 cl=3 min. -12 30 15 4 12 4 1 10 3 1 100 30 70 10000 30 12 24 24 12 65.6
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 1.4v 1.4v dq ck tac toh tohz switching characteristics (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) output load condition v out 50pf 50 w v tt =1.4v dq ck output timing measurement reference point 1.4v 1.4v 30 limits symbol parameter -12 -15 -1539 uni t min. max. min. max. min. max. cl=1 27 27 30 ns tac access time from ck cl=2 9.5 9.5 12 ns cl=3 8 8 9 ns tcac column access time 24.5 24.5 30 ns trac row access time 54.5 54.5 60 ns toh output hold time 3 3 3 ns from ck tolz delay time, output low impedance from ck 0 0 0 ns tohz delay time, output high impedance from ck 3 8 3 8 3 10 ns
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 write cycle (single bank) bl=4 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq x x y d d d d x x tras trcd twr trp trc 31
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 write cycle (dual bank) bl=4 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq xa xa y da da da da tras trcd twr trp db db db db xb xb y trrd tras trcd twr trc 32
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 read cycle (single bank) bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq x x y q q x x tras trcd trp q q tcac trac trc 33
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 bl=4, cl=3 read cycle (dual bank) ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq xa xa y qa qa xa xa tras trcd trp qa qa tcac trac trc xb xb y qb qb qb qb trrd trcd tras tcac trac 34
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 write to read (single bank) bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq x x y d d d d tras trcd q q q q y tcac 35
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 write to read (dual bank) bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq xa xa y da da da da tras trcd qb qb qb qb y xb xb trrd xa xa trcd trp tras twr trc tcac 36
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 read to write (single bank) bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq x x y d d d d trcd q q y tcac tras for output diable twr trac 37
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 read to write (dual bank) bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a1 0 ba dq xa xa y db db db db tras trcd qa qa y xb xb trrd xa xa trcd trp tras twr trc tcac for output disable trac 38
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 write with auto-precharge bl=4 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq x x y d d d d trcd x trc x twr + trp internal precharge starts this timing depends on bl 39
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 read with auto-precharge bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq x x y q trcd q q x tcac trc trac q x trp internal precharge starts @cl=3, bl=4 this timing depends on cl and bl 40
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 auto-refresh ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq trp trc if any bank is active, it must be precharged 41
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 self-refresh entry ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq trp if any bank is active, it must be precharged 42
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 self-refresh exit ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq trc x x internal clk re-start nop or desel 43
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 mode register set bl=4, cl=3 ck /s /ras /cas /we cke dqmb 0-7 a0-9 a10 ba dq trp trsc if any bank is active, it must be precharged mode x x y q q q trcd tcac trac 44
MH1S64CWXTJ-12,-15,-1539 67108864-bit (1048576-word by 64-bit)synchronousdram mitsubishi lsis ( / 45 ) mitsubishi electric oct.28.1996 preliminary spec. some contents are subject to change without notice. mit-ds-0064-0.2 45 outline 1.27 ?.1 133.35 ?.13 3.9max 25.4 ?.13 84 1 127.35 ?.13 17.78 ?.13 3 ?.13 1 ?.13 3 ?.13 2 ?.13 6.35 ?.13 24.495 0.13 8.89 ?.13 29x1.27=36.83 ?.2 42.18 0.13 9x1.27=11.43 ?.2 6.35 ?.1 43x1.27=54.61 ?.2 1.27 ?.1 2-? ?.1 17.78 ?.13 2-r2 ?.13 1 ?.13

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